While I wait for the actual FPGA file (if you have it, please post it here!), could you explain a bit more about the actual issue? I found a thread with your posts which describe the following issue.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/203172.aspx?pi267198=1
"The production 6657 EVM only uses RBL (NO IBL), due to some DSS clock setting issues in PCIE code, the 6657 EVM can’t be enumerated by a Linux or Windows PC using DSS clock. So the 6657 EVM + AMC-PCIE adaptor card can't work in a PC enviornment unless the PC can be configured to generate narrow spectrum 100 MHz PCIE reference clock.
Regards, Eric""
I am rather confused....the older FPGA firmware starts the IBL, just like all the EVM docs state and what I have so far been assuming. You are saying the IBL is no longer used, for any boot mode but I2C. Is this correct? Also, what are these " some DSS clock setting issues in PCIE code" exactly? Which register is affected?
The thread goes on and I find the following post:
"The production 6657 EVM boot directly from RBL (Rom boot loader) in PCIE boot mode, there may be some issue in the PCIE serdes setting in RBL code when using with a PC, typically with DSS clock.
For production 6678 EVM, it boots from IBL (intermediate boot loader) when in PCIE boot mode, the IBL code has some PCIE workaround for this DSS clock issue so 6678 EVM works fine with PC environment.
The EVM is powered from PCIe PCB edge finger connector of the TMDXEVMPCI, no external power supply required.
Regards, Eric"
Again I am confused: this states that the EVM6678 DOEShave the I2C IBL boot followed by RBL boot of the selected flavor. So why is the EVM6657 different from the EVM6678? Especially since the EVM6657 does not boot over PCIe when used with the AMC-PCIE adapter?
I am assuming the DSS clock fix mentioned in the thread above sets the registers "SERDES_CFGx" up differently. However, when looking at the various clock schemes the EVM6657 supports, the one set by the IBL seems to be identical to the one I see set in the PCIe registers with my XDS560. Also, I can see the ROMCode writing them out:
========== RBL:
========== IBL:
"C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c665x\c665xinit.c"
void iblPCIeWorkaround() { UINT32 v, flag_6678 = 0, flag_6670 = 0, flag_6657 = 0, MAGIC_ADDR; UINT32 i; /* Power up PCIe */ devicePowerPeriph (TARGET_PWR_PCIE); for(i=0; i<1000; i++) asm (" NOP"); DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG0), 0x00062320); /* ss clock */ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG1), 0x00022320); /* ss clock */ ... }PCIE_APP_SERDES_CFG0 = 0x00062320 Corresponds with:
- [5] RX_LOS=1,
- [8:6] RX_CDR=4h,
- [12:9] RX_EQ=0001b,
- [13] RX_ENOC=1,
- [15:14] RX_LOOPBACK = 0,
- [16] TX_INVPAIR=0,
- [17] TX_CM=1,
- [18] TX_MSYNC=1,
- [20-19] TX_LOOPBACK=0.
Am I looking at the wrong register? Isn't the SERDES_CFGx register the one wihch determines the PCIe clocking scheme? If RBL and IBL write the same values, what else is the IBL doing that fixes the PCIe boot issue?
Please enlighten me :)
Thanks,
Dirk