Avi,
[quote user="Avi Elbaz"]Pavel, our DDR3 interface is NOT used by the ARM, but the DSP only (ARM is disabled). I'm not sure I follow your reference to a Cortex-DDR issue in the 2.1 advisory.[/quote]
As you are with PG3.0, then this errata is NOT valid for you (may be I was not clear enough in my previous post).
[quote user="Avi Elbaz"]Do you, or don't you have a silicon related issue regarding the DSP and DDR3 interface in silicon version 3.0??[/quote]
No, there are no silicon issues regarding the DSP and DDR3 interface in PG3.0 device.
But I can see these 3.0 usage notes:
2.1.1 DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit
2.1.3 DDR2 and DDR3 Requires Software Leveling
Best Regards,
Pavel