OK, I've written up a walking-ones memory tester that runs on the ARM from L2RAM and tests the DDR. All reads come back with the value 0x0000FFFF regardless of what was written, so it's pretty clear this is an SDRAM issue.
I see a nice 150MHz differential clock on DDR_CLKP and DDR_CLKN, which is the frequency I'm expecting. I see DDR_CS go low and stay low early in the AIS parsing sequence. I see DDR_WR start pulsing low as soon as either the boot ROM is trying to load code into DDR, or the memory tester is doing a write pass. Maybe what I need is a second pair of sharp eyes sanity-checking all those DDR controller register values.