Yi,
Ideally, the power down sequence is the reverse of the power up sequence with the same maximum durations. This eliminates excess electrical stress. Some system designs such as those supporting hot-swap must have gracefull power up and power down sequencing.
The basic power up sequencing timing from rail to rail is 0 to 100ms. This means that you could ramp all of the supplies simultaneously as long as CVDD1 does not exceed CVDD and DVDD15 never exceeds DVDD18 per the comments in the tables in section 7.2.1. Therefore, this also means they can all ramp down simultaneously with the same requirements.
Also see thread: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/270308.aspx
Tom