We have not tested this capability at TI. I would imagine that the 80ps phase offset is fine, as long as the two sources are synchronized in frequency/drift, but I am not certain.
I don't believe anything else needs to be changed or configured to use the line loopback, but you should try to set the PE_SET_CNTL[3:0]=0b1111. You should fully configure the SRIO and SerDes just like normal use, then enable the line loopback. You are able to establish a link (port_ok) and transfer data between the two devices when line loopback is disable correct?
Regards,
Travis