Si Cheng,
The C66x DSP CorePac User Guide explains the cache operation and the answers to your questions, if I understand your questions correctly. Please refer especially to sprugw0 sections 3.3.5 (L1D cache coherence operations) and 4.3.6 (L2 cache coherence operations). Two tables from those, for block coherence operations, are shown below:
If you have additional questions, please continue the thread.
Regards,
RandyP