Steve,
Sorry that I missed your point before. As you may already understand from the other examples in PCIe user guide and PCIe use case app note, the Outbound and Inbound address translation in PCIe is optional abut will be necessary in many cases.
In your example, you can enable Outbound translation in DSP_A and Inbound translation in DSP_B for the PCIe transfer initiated on DSP_A side, such as:
DSP_A:
For Outbound, OB_XLT_EN=1 in CMD_STATUS register (enable OB translation), OB_SIZE=0 (1MB window size by default), OB_OFFSET_INDEX0 = 0xA0000001 (offset=0xA0000000,match BAR1 in DSP_B, OB region 0 is enabled), OB_OFFSET0_HI=0 (no higher 32bit needed).
DSP_B:
For Inbound, IB_XLT_EN=1 in CMD_STATUS register (enable IB translation), BAR1 = 0xA00000008 (match OB_OFFSET in DSP_A), IB_BAR0=1 (choose BAR1 in DSP_B), IB_START0_LO=0x80000000 (match destination in DSP_B), IB_START0_HI=0 (no higher 32bit needed).
Please note the OB_OFFSET address is the PCIe address over PCIe link, it is not related to SoC internal address (0xA0000000 is the 32-bit address chosen randomly, not related to any DDR3 addresses in DSP_A or DSP_B).
After that, the first 1MB of PCIe data space address (0x60000000~0x600FFFFF) in DSP_A will be translated to 0xA0000000~0xA00FFFFF and will be accepted by DSP_B. And the incoming addresses will be translated based on IB registers and remapped to 0x80000000~0x800FFFFF in DSP_B.
For data write from DSP_A's Addr_A to DSP_B's Addr_B, src=0x80000000, dst=0x60000000 for CPU/EDMA initiated PCIe transfer in DSP_A.
For data read from DSP_B's Addr_B to DSP_A's Addr_A, src=0x60000000, dst=0x80000000 for CPU/EDMA initiated PCIe transfer in DSP_A.
It is similar for the PCIe transfer initiated in DSP_B if you enable Outbound translation in DSP_B and Inbound translation in DSP_A.
Again, there are some similar examples and details in PCIe user guide, PCIe use case app note and the PCIe LLD example in MCSDK/PDK package for data transfer/address translation usage. Hope they could help.
