About a UBL. I'm not using any OS. Only my code and a bare metal.
Intersting thing. I'd checked a command sequence into generated .bin file and notice that command for DDR controller configuring is appeared firstly (SDCR, SDRCR etc). Maybe first command (after PLL configs) must be a PSC command for DDR controller turning on? I' tried to insert such command into .bin using WinHex editor but DDR not initialized. I think to attempt to add additional PSC commands corresponded to initialization sequence from "OMAP-L138 DSP+ARM Processor Technical Reference Manual".
This is the dump that I got by debug GEL file. I'd used my .cfg file and ARM project only. Booting was success cause ARM code allocates into SharedRAM but DDR still not initialized (I need DDR for large DSP project).
ARM9_0: GEL Output:
---------------------------------------------
ARM9_0: GEL Output: | Device Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_02 = 0x0000000C
ARM9_0: GEL Output: DEV_INFO_03 = 0x00000033
ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6521316-2-12-28
ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 3,0,0,1791
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output:
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_20 = 0x30303864
ARM9_0: GEL Output: DEV_INFO_21 = 0x3830306B
ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
ARM9_0: GEL Output: -----
ARM9_0: GEL Output: DEV_INFO_24 = 0x0201C00C
ARM9_0: GEL Output: DEV_INFO_25 = 0x006381E4
ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
ARM9_0: GEL Output: DEV_INFO_26 = 0x0DFE0003
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | BOOTROM Info |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: ROM ID: d800k008
ARM9_0: GEL Output: Silicon Revision 2.1
ARM9_0: GEL Output: Boot pins: 12
ARM9_0: GEL Output: Boot Mode: SPI1 Flash
ARM9_0: GEL Output:
ROM Status Code: 0x00000000
Description:ARM9_0: GEL Output: No error
ARM9_0: GEL Output:
Program Counter (PC) = 0x80008C18
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | Clock Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLLs configured to utilize crystal.
ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
ARM9_0: GEL Output:
ARM9_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
ARM9_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware
ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
ARM9_0: GEL Output: and then reload.
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | PLL0 Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
ARM9_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
ARM9_0: GEL Output: PLL0_SYSCLK3 = 25 MHz
ARM9_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
ARM9_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
ARM9_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
ARM9_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | PLL1 Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
ARM9_0: GEL Output: PLL1_SYSCLK2 = 150 MHz
ARM9_0: GEL Output: PLL1_SYSCLK3 = 100 MHz
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | PSC0 Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: State Decoder:
ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
ARM9_0: GEL Output: >3 = Transition in progress
ARM9_0: GEL Output:
ARM9_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3
ARM9_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3
ARM9_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3
ARM9_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
ARM9_0: GEL Output: Module 4: SPI 0 STATE = 3
ARM9_0: GEL Output: Module 5: MMC/SD 0 STATE = 3
ARM9_0: GEL Output: Module 6: AINTC STATE = 3
ARM9_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
ARM9_0: GEL Output: Module 9: UART 0 STATE = 3
ARM9_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
ARM9_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
ARM9_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
ARM9_0: GEL Output: Module 13: PRUSS STATE = 0
ARM9_0: GEL Output: Module 14: ARM STATE = 3
ARM9_0: GEL Output: Module 15: DSP STATE = 3
ARM9_0: GEL Output:
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output: | PSC1 Information |
ARM9_0: GEL Output: ---------------------------------------------
ARM9_0: GEL Output:
ARM9_0: GEL Output: State Decoder:
ARM9_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
ARM9_0: GEL Output: 1 = SyncReset (reset assered, clock on)
ARM9_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
ARM9_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
ARM9_0: GEL Output: >3 = Transition in progress
ARM9_0: GEL Output:
ARM9_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3
ARM9_0: GEL Output: Module 1: USB0 (2.0) STATE = 3
ARM9_0: GEL Output: Module 2: USB1 (1.1) STATE = 3
ARM9_0: GEL Output: Module 3: GPIO STATE = 3
ARM9_0: GEL Output: Module 4: UHPI STATE = 3
ARM9_0: GEL Output: Module 5: EMAC STATE = 3
ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3
ARM9_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3
ARM9_0: GEL Output: Module 8: SATA STATE = 3
ARM9_0: GEL Output: Module 9: VPIF STATE = 0
ARM9_0: GEL Output: Module 10: SPI 1 STATE = 3
ARM9_0: GEL Output: Module 11: I2C 1 STATE = 3
ARM9_0: GEL Output: Module 12: UART 1 STATE = 3
ARM9_0: GEL Output: Module 13: UART 2 STATE = 3
ARM9_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 3
ARM9_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 3
ARM9_0: GEL Output: Module 16: LCDC STATE = 0
ARM9_0: GEL Output: Module 17: eHRPWM (all) STATE = 3
ARM9_0: GEL Output: Module 18: MMC/SD 1 STATE = 3
ARM9_0: GEL Output: Module 19: UPP STATE = 0
ARM9_0: GEL Output: Module 20: eCAP (all) STATE = 3
ARM9_0: GEL Output: Module 21: EDMA3 TC2 STATE = 3
ARM9_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
ARM9_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
ARM9_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
ARM9_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
ARM9_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
ARM9_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
ARM9_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
ARM9_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3