Tom,
Thanks for the continued assistance but I think we are not on the same wavelength anymore. I already have a repeatable DDR3 configuration for these boards, and have been using it for at least 6 months with out any problems. I am trying to figure out why a small number of boards don't work after the RBL. Also, the GEL does contain leveling in a funciton called DDR3Leveling() that executes Full Automatic leveling, I split it apart for debugging purposes.
To go back to question 4, According to the DDR3 UG a complete DDR3 SDRAM initialization sequence should only happen after a hard or soft reset, or a write to SDCFG (section 2.11). So it should not matter what INITREF_DIS is set to when the timing registers are written (unless this is also not accurate in the UG).
I am trying to rule out any hardware issues with the boards, because if there are any we need to do another revision. If is just a problem with the RBL, I can solve it in software.
Mark