Forum Post: Understanding Timing Diagram of VPIF

Image may be NSFW.
Clik here to view.

  Hi,

   I wanted to understand certain terminologies used in Raw Capture Progressive Mode:

a. Vertical Blanking , min = 3lines                  ---------- Is it same as telling it needs a minimum of 3 rows

b. Horizontal Blanking, min = 21 clk              ---------- Is it same as telling it needs a minimum of 21 VP_CLK0 and 1 input clk or is it mentioned in number of rows.

c. Frame Blanking, min = 369 clk                   --------- ???????????????

d. Valid data period, min= 2 clk                      ---------- Why is it less than horizontal blanking period ? and what it is ?

Below is the timing diagram of Digital video port of OV2643

Image may be NSFW.
Clik here to view.

Image may be NSFW.
Clik here to view.

Also the master clock generated by CDCE913PW on UI board generates normal pulse of 24.0000080 Mhz

while VP_CLKIN0 and 1 are driven by 48 Mhz PCLK generated by camera module, its shape is saw tooth form.

Does the wave form shape of VP_CLKIN 0and 1 affect the VPIF ???