Mark,
This forum post is for C6654. We have recently found that the C665x GEL does not provide all of the registers needed to properly enable Partial Automatic Leveling. The GEL provided successfully works at DDR3-800 but is not robust at higher speeds. Your GEL appears to configure the DDR3 interface for DDR3-1066.
We are currently updating the DDR3 Init App note and the DDR3 UG to reflect these changes. These documents will be released by the end of January. You will need to add the following to your GEL file:
#define DDR3_CONFIG_REG_52 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D4))
#define DDR3_CONFIG_REG_53 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D8))
#define DDR3_CONFIG_REG_54 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04DC))
#define DDR3_CONFIG_REG_55 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04E0))
#define DDR3_CONFIG_REG_60 (*(unsigned int*)(CHIP_LEVEL_REG + 0x04F4))
DDR3_CONFIG_REG_52 |= 0x00000200;
DDR3_CONFIG_REG_53 |= 0x00000200;
DDR3_CONFIG_REG_54 |= 0x00000200;
DDR3_CONFIG_REG_55 |= 0x00000200;
DDR3_CONFIG_REG_60 |= 0x00000200;
The above registers are written where the DDR3_CONFIG_REG_23 register is written to enable Partial Automatic Leveling in the initialization sequence for C667x devices.
I also noticed that your GEL file initialized the wrong INIT_RATIO registers. We need to clarify this in the DDR# UG as well for C665x. Please see the correct registers below:
DATA0_WRLVL_INIT_RATIO = 0x2C;
DATA1_WRLVL_INIT_RATIO = 0x2C;
DATA2_WRLVL_INIT_RATIO = 0x3A;
DATA3_WRLVL_INIT_RATIO = 0x33;
DATA8_WRLVL_INIT_RATIO = 0x1C;
DATA0_GTLVL_INIT_RATIO = 0xA4;
DATA1_GTLVL_INIT_RATIO = 0xA4;
DATA2_GTLVL_INIT_RATIO = 0xB1;
DATA3_GTLVL_INIT_RATIO = 0xB7;
DATA8_GTLVL_INIT_RATIO = 0x98;
We apologize for the confusion. We are diligently working to get the documentation corrected.
Tom