David,
Thanks for your reply, that is pretty much what we are doing, here is what we are doing associated with your suggestions.
1) The code loaded (for the other cores) are in DDR3 memory or the first half of L2SRAM (0x1n800000-0x1n87FFFF on a 6670 for each core).
2) We do not have issues loading and starting the cores initially, however when we are trying to reload the core (with a different or the same program) that is where our issue is coming about. This is our procedure to try to load the cores with something different:
a) Put the core into reset using LRSTZ in MDCTL
*((volatile unsigned int *)(0x02350A58 + (8 * core))) &= ~(1 << 8);
b) Load the program via SRIO (not overlapping the reserved section the bootloader uses) and set the Boot Magic Address to the start of the program.
c) Take the core out of reset
*((volatile unsigned int *)(0x02350A58 + (8 * core))) |= (1 << 8);
d) Delay to allow ROM Bootloader to start up
e) Send IPC to core to jmp to address (same way you do)
3) The test program is just a while loop that increments data at a DDR3 location (outside of the code space), one program running out of L2, one out of DDR3 so we can test the loading of the core.
The first loading of the slave cores always works, however after the second load (of core 1 especially) after all 3 cores have been loaded and running all the L2 of that core gets trashed. I've looked at it before issuing the IPC to start the core, but after the Reset was released, and this is where it seems to be trashed.
If I am doing anything wrong on my reload sequence, please let me know.
Thanks,
Erick