Forum Post: PLL mult/div Limitations DM368

I'd like to know what are the limitations on frequency values on all steps of PLL configuration for DM368:

1. Is there a low limit on the PLL input clock (OSCIN / PRE-DIV)?
2. What is the high limit on the PLL output clock (before POST-DIV)?

I'm using the following settings:

Input clock: 27 MHz (from an oscillator).

PLL1:

PLL1_PREDIV = 9;

PLL1_PLLM = 113;

PLL1_POSTDIV = 1;

PLLOUT1= 27 / 9 * 2 * 113 / 1 = 678 MHz

PLL2:

PLL2_PREDIV = 2;

PLL2_PLLM = 16;

PLL2_POSTDIV = 1;

PLLOUT2= 27 / 2 * 2 * 16 / 1 = 432 MHz

Is there anything wrong with those settings? I have a custom device exhibiting variations in performance from board to board.

Thanks.