Hello people.
I have an issue about PCIe communication between a C6678 EVM and Xilinx Spartan 6 EVM. I'm connecting a TMDXEVM6678L EVM to Xilinx SP605 EVM on PCIe port. In this set, DSP is RC and FPGA is EP. I'm running the PCIe example code in C6678 PDK coming with MCSDK 2.0 without any modification (I only modified PCIe mode variable as RC_mode, necessarily)
I have four Advantech TMDXEVM6678L EVM boards. One of them is Rev. 2.0 and the others are Rev. 3.0. I'm using them with exactly same configuration, I mean the configuration switches on board (I enable PCIESS, set reference clock as the clock source on board). When I connect Rev.2 one, link training part is done and link is up, but with the Rev. 3 one, I stuck at the link training part forever. I tried to change to another Rev.3 board but the result is same.
So my question is, what is the difference between these revisions of EVM's that affecting the PCIESS usage?