Hello Elias,
If CPU interrupt enable bit ( bit 13 in TCR2) . The DMA channel is capable of generating a CPU interrupt when a block transfer is finished. and regarding the status bit in TCR2.
The DMA controller clears the STATUS bit to 0 if:
• All the bytes specified by LENGTH in DMACHmTCR1 have been transferred.
• A value of 0 is written to LENGTH in DMACHmTCR1.
If all the bytes are transfer as specified by the length then the status bit will be set to '0', unless auto reload bit is set and the next transfer has began.
If the above condition is true (auto reload bit set and start of subsequent transfer) then the status reading status bit can reflect '1'.
Hope the above helps you to resolve the your issue. Please let m e us know if you have further question on this.
Regards
Vasanth