To use LDREX/STREX, it requires the global monitor. The global monitor in the interconnect is not implemented in KS2, but even then you’d need the MMU on.
Looking at the TRM:
External global monitor
If synchronization primitives are used for memory pages that are Strongly-ordered, Device, or Inner-Shareable Normal Non-Cacheable, a global monitor must be provided in the interconnect. See the ARM Architecture Reference Manual for more information. The memory requests are sent on the AXI interface as Read-Exclusive or Write-Exclusive. See the AMBA AXI Protocol Specification for more information.
Note
• Use of synchronization primitives on addresses in regions marked as Strongly-ordered or Device is UNPREDICTABLE in the ARMv7-A Architecture. Code that makes such accesses is not portable.
• Load-Exclusive and Store-Exclusive requests are not supported to shareable Normal Write-Through memory.
• Load-Exclusive and Store-Exclusive requests are not supported to shareable Normal Write-Back memory if the cache is disabled, SCTLR.C is 0.
It is suggested that the exclusives is not used in non-cacheable situation. The caching subsystem implements them. If MMU is off one needs to use other instructions and manually ensure exclusivity is sharing.