Is the noise present on all the different DDR interfaces, or specific to one? Is the noise specific to a DQS pair? What layers are the signals routed on and what layers are GND planes (assuming you have solid GND planes)? What via types are used (micro-vias or drill vias)?
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Forum Post: RE: TDA4AH-Q1: DDR CLK Certification
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Forum Post: RE: AM68A: pcie does not generate clock output
Hi Yuli, Thanks for the very interesting results. I had assumed the ti,syscon-pcie-refclk-out update was enough, since I modified TI EVM to use internal clock and was getting clock out when checking with a scope... but perhaps somehow the external clock was still driving the SERDES on the SoC and/or PCIe slot. Will be trying out some experiments like removing the clock generator completely from the board, since I suspect the mis-wiring errata is causing the external clock to somehow get routed to the SERDES module on the TI EVM even after I made some board modifications. But again, thank you for trying out the experiment and sharing your results. Regards, Takuma
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Forum Post: RE: AM5728: Hiss Noise in TLV320AIC34 Audio Codec With AM5728
Hello Viijay, This use case is not something that is covered by our SDK. Please look for assistance within the open source community. See: https://www.alsa-project.org/wiki/Main_Page https://alsa.opensrc.org/ Also take a look at our tech support disclaimer: https://software-dl.ti.com/processor-sdk-linux/esd/AM57X/09_02_00_133/exports/docs/linux/Overview_Technical_Support.html#open-source-software-support-disclaimer -Josue
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Forum Post: RE: AM3358: porting linux on AM3558
I'd recommend to start with AM335x Linux SDK and online guide https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM335X https://software-dl.ti.com/processor-sdk-linux/esd/AM335X/09_01_00_001/exports/docs/linux/Overview.html Best, -Hong
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Forum Post: AM6442: what EQEP registers to set for the case of the gated Index input HIGH for the duration while the B input is low ?
Part Number: AM6442 I am looking at the AM64X TRM Table 12-4409 and the registers, but I cannot the index input phase detection setting for an encoder when the gated Index input is HIGH for the duration while the B input is LOW - please help specify the setting. (I cannot find the index setting on the MCU+ SDK's EQEP capture example.)
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Forum Post: RE: AM62A7: C7000 compiler code instability on C7504 core
Hi Arya, Would you please help me understand the issue in more details. 1. Does the compiler successfully compile the code? Did it produce a binary? 2. You mentioned that compiler version 3 is more stable than version 4. Do you mean that 4 does not compile the code? or do you mean that both compile the code but the code does not produce the same results. If that is the case, can you provide examples of when you have inconsistent results? Best regards, Qutaiba
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Forum Post: RE: AM62A7: Frequency Drop in the SDK Version 9.00.01.03
Hi Ann, Are you using TI EVM board or is this on your customer built board? Best regrads, Qutaiba
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Forum Post: RE: AM3354: AM3354
Hi, sorry for the delay, I requested more samples to be produced. Below measurements. Red - VBUS1 Blue - DM Green - DP
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Forum Post: RE: AM62A7: DCC profile generation tool for AM6xA ISP
Hi Peng, [quote userid="576360" url="~/support/processors-group/processors/f/processors-forum/1361229/am62a7-dcc-profile-generation-tool-for-am6xa-isp/5201972#5201972"]I cannot locate which files are causing the problem by comparing their differences.[/quote] It looks like you used a specially made rgb2rgb xml file which is not supported by DCC. Please merge your pervious changes under "imaging/algo/dcc/" to support that.
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Forum Post: RE: TDA4AH-Q1: DDR CLK Certification
We only have an interposer on the DDRSS0 interface and not the DDRSS1 interface, so we have not been able to look at DDRSS1. The DQS pairs toggle at the same time as shown in the picture so I cant say if it is specific to one pair. Our stack up and routing is as below. We are using a 4-6-4 stack up so a combination of both types of vias are used. Via stubs are kept within the LPDDR4 layout spec limit. Top L2 -> Ground Plane L3 L4 -> Ground Plane L5 -> Ground Plane L6 -> CLK and Control routing L7 -> 1V1 plane L8 -> Ground Plane L9 -> Ground Plane L10 -> Bytes 0 and 2 routing L11 -> Ground Plane L12 -> Bytes 1 and 3 routing & CLK/Control signals T-Branch L13 -> Ground Plane L14 -> DDR IC
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Forum Post: RE: CODECOMPOSER: Run SonarQube with Build Wrapper in Windows.
Hello, I don't have any experience with SonarQube so I can't provide much insight here. However, in the examples, it looks like the build utility and not the compiler executable itself is being wrapped. If you are working with the CCS build system, then would you not need to reference gmake? See the below chapter in the CCS User's Guide for more information on the build system in CCS: https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_project-management.html#build-rebuild-project Thanks ki
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Forum Post: RE: TDA4VM: Two difference ways to use this device for AI model
Hello Josel, Yes, this is correct. For more on what is supported on this device, see the following: RTOS SDK Documentation: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_02_00_05/exports/docs/psdk_rtos/docs/user_guide/release_notes_09_02_00_j721e.html EDGEAI-TIDL-TOOLS Github: https://github.com/TexasInstruments/edgeai-tidl-tools?tab=readme-ov-file#tidl---ti-deep-learning-product Thank you, Fabiana
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Forum Post: RE: DRA821U: Having Problem Booting U-Boot Using SDK 9.02
Keerthy, I built the EVM U-Boot images today using the instructions located here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j7200/09_02_00_04/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html The images I built loaded and ran successfully (WKUP_UART for the R5, MAIN_UART0 for A53). Lewis would like to load both the R5 and A53 images through WKUP_UART on his custom board (he doesn't have access to MAIN_UART0). But I would like to confirm that he can at least do the out of box experience on WKUP_UART and MAIN_UART0 with the EVM first. Once this is working, I think the next step is to try and boot with WKUP_UART only on the EVM. Only once this is verified to work should we move on to the custom board. I don't want to be debugging multiple potential issues at once, best to divide and conquer. Thanks, Stuart
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Forum Post: RE: AM625: Boot Stall and Crashes
Hi Franz, We are preparing the instructions for you to dump the SYSFW debug trace in the pass and failure cases. Does your board have WKUP_UART or JTAG access? The debug trace can be dump from one of the interfaces.
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Forum Post: RE: AM623: SDK9.2 UART boot hang and reset if doesn't stop
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/boot/Kconfig?h=09.02.00.010#n1225 It looks like by default, the u-boot ".config" would have CONFIG_AUTOBOOT=y CONFIG_BOOTDELAY=2 So to disable autoboot, run "make menuconfig..." to re-build u-boot configuration, and either disable AUTOBOOT or set BOOTDELAY=-1 from the menu. Best, -Hong
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Forum Post: TDA4VH-Q1: Ethernet EMOS Camera Integration
Part Number: TDA4VH-Q1 Hello, We are trying to configure an ethernet EMOS camera with TDAH board and was curious if you could share with us some resources that would help us get started with the task. We are most interested in understanding how we can capture the frames out of the recorded H.264 format video sequence received.
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Forum Post: RE: SK-TDA4VM: Edge AI GST Apps HWA VPAC_LDC Fail
Hello, W hich SDK version are you using? Based on your pipeline, it seems like you are using the IMX390 sensor which requires three DDC binaries to be included in your pipeline similar to this input pipeline: gst-launch-1.0 v4l2src device=/dev/video-imx390-cam0 ! queue leaky=2 ! video/x-bayer, width=1936, height=1100, format=rggb12 ! tiovxisp sink_0::device=/dev/v4l-imx390-subdev0 sensor-name=SENSOR_SONY_IMX390_UB953_D3 dcc-isp-file=/opt/imaging/imx390/linear/dcc_viss.bin sink_0::dcc-2a-file=/opt/imaging/imx390/linear/dcc_2a.bin format-msb=11 ! video/x-raw, format=NV12 ! tiovxldc dcc-file=/opt/imaging/imx390/linear/dcc_ldc.bin sensor-name=SENSOR_SONY_IMX390_UB953_D3 ! video/x-raw, format=NV12, width=1920, height=1080 ! tiovxmultiscaler Thanks, Fabiana
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Forum Post: AM62A7: meta-edgeai defines a custom wks file which changes the boot and rootfs partition names
Part Number: AM62A7 I'm not sure if there is a mailing list for meta-edgeai so posting here. Is there any reason for meta-edgeai to have its own wks file? I'm mostly upset that it changes the standard "boot" partition to "BOOT" and "root" partition to "rootfs" which breaks all my scripts and all our standard instructions now have to be different when booting the edgeai image vs the base/default images. This also mounts the boot partition over the kernel /boot directory. This was fixed recently in the meta-ti wks images. git.ti.com/.../
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Forum Post: RE: AM62A7: meta-edgeai defines a custom wks file which changes the boot and rootfs partition names
[quote userid="153510" url="~/support/processors-group/processors/f/processors-forum/1363454/am62a7-meta-edgeai-defines-a-custom-wks-file-which-changes-the-boot-and-rootfs-partition-names"]This also mounts the boot partition over the kernel /boot directory. This was fixed recently in the meta-ti wks images.[/quote] Correction I was wrong, it is just fixed in a way I wasn't expecting. It disables fstab updates in the recipe, see the above linked commit for a cleaner solution. WKS_FILE = "tisdk-edgeai-sdimage.wks" WIC_CREATE_EXTRA_ARGS += " --no-fstab-update"
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Forum Post: RE: AM62A7-Q1: Gstreamer pipeline performance issues with tiovx plugins
Hi Jingjie, We have a TIOVX apps framework that allows you to build image processing pipelines on top of TIOVX. This approach can give you a better performance than GStreamer based pipeline. I would recommend you to give it a try. You can find examples at: https://github.com/TexasInstruments/edgeai-tiovx-apps/tree/main/tests . Regards, Jianzhong
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