Hi Pramod Kumar Swami - We tried the ONNX RT, still it shows transpose was failed to offload. Please check the logs
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Forum Post: RE: SK-AM62A-LP: Requesting patch to offload multiple operators to MMA for version 9.2 edgeAI
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Forum Post: RE: AM625: interrupt index
Hello Tony, Thanks for your query. I have taken your inputs and working on it. Please allow some time to revert back. Regards, Tushar
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Forum Post: RE: AM6548: ATF: Unhandled Exception in EL3 when running from DDR4, and DDR4 Questions
Hi James, quick question about reading the MR registers using DDRCTL_MRCTRL0/1/2. I cannot seem to get it to work. The following is the code I use to do it: void ddr_dump_mr_regs (struct am654_ddrss_desc *ddrss) { volatile int regVal = 0; // Read from all DDR MR registers for (int i = 0; i 0) { regVal = ddrss_ctl_readl(DDRSS_DDRCTL_MRCTRL0); } printf("MR%d val: 0x%08x \n", i, ddrss_ctl_readl(DDRSS_DDRCTL_MRCTRL1)); } } We are only single rank here, with 2 devices. But MRCTRL1 seems to always return 0. Upon reading the TRM, it seems that MRCTRL1 is only for "Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes.". So is there anywhere we can actually read the MR registers? And are these MR registers different from the DDRPHY_MR0-7_DDR4 registers? Could we not just read from those? Thanks, Ben
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Forum Post: RE: AM62A7: AM62A DDR reserved-memory
Hello Ren, Thanks for reaching out to Texas Instruments E2E support forum. I have taken your inputs and working on it. Please expect a reply in few business days. Regards, Tushar
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Forum Post: RE: AM69A: Inference with compiled model fails on device, but is succesful on x86.
Yes, that's all correct. model, script and artifacts folder attached in zip If you need anything else please let me know. Thanks very much e2e.ti.com/.../tidl_5F00_test.zip
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Forum Post: RE: PROCESSOR-SDK-AM64X: Flash into eMMC over Ethernet
I am not planning to use A (linux) core, only R cores (bare metal) are going to be booted up - FYI
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Forum Post: RE: TDA4VE-Q1: Vision apps
Hi Nikhil, [quote userid="506459" url="~/support/processors-group/processors/f/processors-forum/1360511/tda4ve-q1-vision-apps/5191141#5191141"] Could you please confirm if you have downloaded the test data and models required for this application? [/quote] Yes, I have downloaded the data set and I am not aware of the models. Following are the commands that I have used to set up QNX SDK and vision apps //shorten terminal folder PS1='${debian_chroot:+($debian_chroot)}\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\W\[\033[00m\]\$ ' //install TI SDK RTOS on the below folder //set SDK RTOS path PSDK_RTOS_PATH=/home/$USER/ti/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06 //${PSDKR_PATH} refers to the path where Processor SDK RTOS (PSDK RTOS) is installed PSDKR_PATH=/home/$USER/ti/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06 //needed for QNX SPL boot PSDKL_PATH=/home/$USER/ti/ti-processor-sdk-linux-adas-j721s2-evm-09_01_00_06/ //TI SDK RTOS and QX version should be same SDK RTOS : 09.01.00.06 QNX : 7.1.0 //extract and install SDK tar -xvf ti-processor-sdk-qnx_j721s2_xx_xx_xx.tar.gz -C $PSDK_RTOS_PATH tar -xvf ti-processor-sdk-qnx_j721s2_09_01_00_06.tar.gz -C $PSDK_RTOS_PATH //set QNX env variables source /home/$USER/qnx710/qnxsdp-env.sh //build RTOS SDK and install dependencies cd ${PSDK_RTOS_PATH} ./sdk_builder/scripts/setup_psdk_rtos.sh //set QNX BSP environment variables #The location of the extracted bsp that was downloaded from QNX Software Center QNX_BSP_PATH=${QNX_BASE}/bsp/ #The QNX BSP zip file QNX_BSP_NAME=BSP_ti-j721s2-tda4vmeco-evm_br-710_be-710_SVN970946_JBN9.zip QNX_BSP_VERSION=710_SVN970946_JBN9 #set QNX path in TI SDK PSDK_QNX_PATH=$PSDK_RTOS_PATH/psdkqa cd $PSDK_QNX_PATH ./psdk_qnx_setup_qnx710.sh //Build steps / set the environment variables QNX_SDP_VERSION=710 QNX_BASE=/home/$USER/qnx710 BUILD_QNX_MPU=yes PROFILE=release BOARD=j721s2_evm SOC=j721s2 cd sdk_builder ./make_sdk.sh cd ${PSDK_QNX_PATH}/qnx //qnx build with "N" number of threads make all -j4 make all -j20 make qnx_fs_create //calib-touch missing, //libfontconfig.so missing ,resolved by searching in following link and installing //Modify the following lines BUILD_EMULATION_MODE=no BUILD_TARGET_MODE=yes BUILD_LINUX_MPU=no BUILD_QNX_MPU=yes PROFILE=release //flashing QNX OS umount /dev/sdb1 umount /dev/sdb2 umount /dev/sdb3 cd ${PSDKR_PATH} sudo sdk_builder/scripts/mk-qnx-card.sh --device /dev/sdb // mount the SD card using GUI and then give this cmd //copy binaries from sdcard make qnx_fs_create_sd //copying the vison apps data set cd /media/$USER/qnxfs/ mkdir -p vision_apps cd vision_apps tar --strip-components=1 -xf /home/rajan/ti/psdk_rtos_ti_data_set_09_02_00.tar.gz tar --strip-components=1 -xf /home/rajan/ti/psdk_rtos_ti_data_set_09_02_00_j721s2.tar.gz psdk_rtos_ti_data_set_09_02_00/ sync //To run the vision apps in qnx cd /ti_fs/vision_apps . ./vision_apps_init.sh [quote userid="506459" url="~/support/processors-group/processors/f/processors-forum/1360511/tda4ve-q1-vision-apps/5191141#5191141"] I believe you missed out to mention the errors. Could you elaborate? [/quote] The errors that I am mentioning are undefined environment variables, TIAMCGT_ROOT GCC_SYSBIOS_ARM_ROOT GCC_WINDOWS_ROOT (I am using ubuntu 22.04 with gcc installed; I can ignore this one.) undefined TIARMCGT_ROOT= file TIARMCGT_LLVM_ROOT=$(PSDK_TOOLS_PATH)/ti-cgt-armllvm_3.2.0.LTS undefined GCC_SYSBIOS_ARM_ROOT= file CGT6X_ROOT=$(PSDK_TOOLS_PATH)/ti-cgt-c6000_8.3.7 file CGT7X_ROOT=$(PSDK_TOOLS_PATH)/ti-cgt-c7000_3.1.0.LTS undefined GCC_WINDOWS_ROOT=
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Forum Post: RE: AM3359: Excessive Sync0 Jitter Seen Between Boards
So I can read ESC revision from ESC registers 0x00 and 0x01. They read 1 and 997 before I update the .bin and .h files, and then read 1 and 1267 after I update them. But I see the same behavior with both versions
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Forum Post: TDA4AH-Q1: DDR CLK Certification
Part Number: TDA4AH-Q1 Other Parts Discussed in Thread: J784S4XEVM While testing the DDR CLK on our custom board to meet JDEC compliance there are failures whenever data is being transferred. As can be seen on the scope captures, whenever there is activity on the DQS line the single ended clock lines get affected. This is causing the single ended clock certification tests to fail. At first we thought it may have been power delivery related but after measuring the 1V1 line on the decoupling caps of both the processor and DDR IC there is no ripple seen. It also appears as if it could be cross talk but the only adjacent lines to the CLK in our layout are address lines and it does not appear to be coming from those. We tried to follow the EVM (J784S4XEVM) layout and decoupling scheme as much as possible and also referenced the the layout guidelines found here www.ti.com/.../spracn9e.pdf Is there any other reasons the clock lines may be behaving like this or are there any other designs that have experienced this behavior?
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Forum Post: RE: AM6442: HW breakpoints
I believe Dominic is correct regarding hardware breakpoints/watchpoints. I will look to confirm.
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Forum Post: RE: AM5728: PCIe_wSOcLib_arm_example is getting stuck at "Starting link training..." .
Hi Phaneesh, Could you check DIP switch settings to see if AM57 is in EP mode on the EP device, and RC mode on RC device as documented in SDK docs: https://software-dl.ti.com/processor-sdk-linux/esd/AM57X/09_02_00_133/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_End_Point.html Regards, Takuma
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Forum Post: RE: AM62A7: DCC profile generation tool for AM6xA ISP
Hello Peng Qiang, [quote userid="576360" url="~/support/processors-group/processors/f/processors-forum/1361229/am62a7-dcc-profile-generation-tool-for-am6xa-isp"] 3.Then enter sensor driver folder and run the "generate_dcc.sh" script from there.At this point, there is a problem of not being able to produce the image [/quote] The PRJ_DIR folder must be under imaging/sensor_srv/src, for example, ../../../sensor_drv/src/X3C. [quote userid="576360" url="~/support/processors-group/processors/f/processors-forum/1361229/am62a7-dcc-profile-generation-tool-for-am6xa-isp"]5.At this point, there is an issue: Uable to init TIOVX module.As shown in the following figure.[/quote] Would you mind sharing your complete GStreamer pipeline? In addition, have you validated receiving raw data from the sensor using yavta or v4l2 utility? Regards, Jianzhong
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Forum Post: RE: PROCESSOR-SDK-AM62X: USE TWO INDEPENDENT DISPLAY
Okay, that makes sense because you have weston running and it extends both your displays by default. If you want to drive two independent screens with two different contents, you need to write your custom userspace application. Regards, Krunal
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Forum Post: RE: AM623: Secure boot Implementation
Thanks for your interests on AM62x SoC. We have AM62x security resource download portal, where security collaterals/links/tools... are hosted https://software-dl.ti.com/secure/software/sitara-sec/AM62X-RESTRICTED-SECURITY/AM62x_HS_index_FDS.html User may request access to AM62x security resource download portal https://www.ti.com/licreg/docs/swlicexportcontrol.tsp?form_id=337827&prod_no=AM62X-RESTRICTED-SECURITY&ref_url=ep_processors_Sitara-MPU Hopefully the collaterals would clarify your questions. Best, -Hong
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Forum Post: RE: SK-AM62: AM62x kmscube, gpu initialization
There is no GPU initialization problem and here is overall summary: Upon boot, we cannot control which device, GPU or DSS, will get probed first and who ever gets probed first will get /dev/dri/card0 assigned. In general, your userspace application needs to query the /dev/dri device, identify the GPU or DSS card and create the appropriate application APIs. kmscube does not have such logic but the developers of kmscube allow their users to pass the /dev/dri card through the --device option. On the other hand, weston will go query your display card upon boot and use the appropriate /dev/dri/card node upon booting. In summary, your custom application needs to query the display device as part of it's init logic. Regards, Krunal
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Forum Post: RE: SK-TDA4VM: How can I enable and debug IMX390, DS90UB953 and DS90UB960 with Edge AI SDK?
Could you try using k3-j721e-fpdlink-imx390-cm-0-0.dtbo ? Thank you, Fabiana
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Forum Post: RE: PROCESSOR-SDK-AM62X: Does TEVI-OV5640-C-S84-IR-RPI15 supports TI custom AM625 SOM ?
This is an IR camera and won't need an ISP, right? If that's the case, it should work on AM62x which doesn't have an ISP.
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Forum Post: RE: CCSTUDIO: THEIA: how to create a new System project for AM6x from scratch that has sysconfig pre-populated
Nick: that MCU+ SDK team stance seems odd given Kai has stated CCS v12 is the last "old" Eclipse IDE based version. Appears there may be a support disconnect between the CCS & the MCU+ SDK team that is concerning. (Kai - I hope you are seeing this.)
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Forum Post: RE: AM6442: Using UDMA for continuous slave McSPI transfer
Hello Angel, Sorry for delayed replies. I was on leave yesterday and was on training last week. We can continuously discuss this topic. So, my first question is that May I know why you enabled TX as well ? Do you need to transfer data to ADC from SOC ? If this is the case, then what is your Tx and RX pins? How did you configure them in the system config? My suggestion is that we can try to stick with the MCSPI+PKTDMA and don't go with BCDMA since, as you mentioned, UDMA chapter is difficult and will take more time to solve the issues if we get during implementation and don't have an examples . I understand your concern, so if you look at the driver dma_write/dma_read api, it's typically a combination of channel initiizations and then start DMA for each channel. After completion of DMA channels we are closing the channels.Again, when you need to start DMA again we, are initilizting the channels and starting the DMA. Here, you can notice every time why we need to initialize the channels in your case. So, we can skip the teardown and initializations of channels in the driver for every each DMA start and completion respectively . And, for DMA, start and completion are typically done with the udma_queraw and udma_dequeraw functions, which are typically controlling DMA registers and do not take that much time. Conclusion , we will use the udma_queraw and udma_dequeraw functions for every DMA start and completion and will initialize the DMA channels for only one time. Please share the answers for above queries .Based on this, I can share the suggestions for the driver updates. [quote userid="584118" url="~/support/processors-group/processors/f/processors-forum/1356910/am6442-using-udma-for-continuous-slave-mcspi-transfer/5188585#5188585"]According to TI's own papers, it takes at least 7us to do that.[/quote] Can you please point out the documentation for above one ? Regards, Anil.
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Forum Post: RE: TDA4VM: EthFW - MAC 2: SERDES PLL is not locked
Hello Steve, Looks like the error may be due to the hardware setup. Do you have the J721E Quad-Port Eth Expansion Board connect to the J721E EVM board as described here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_01_00_06/exports/docs/ethfw/docs/user_guide/ethfw_c_ug_top.html#ethfw_depend_evm_quadport_j721e Thanks.
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