I tried the loopback in \ti\pdk_keystone2_3_00_01_12\packages\exampleProjects\hyplnk_K2HC66BiosExampleProject_00_01_12,
The serdes only support 156.25MHz ref clock and 6.25G data rate, so the setting is:
#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG
//#define hyplnk_EXAMPLE_REFCLK_156p25
//#define hyplnk_EXAMPLE_REFCLK_250p00
//#define hyplnk_EXAMPLE_REFCLK_312p50
/*****************************************************************************
* Select internal loopback or use the SERDES connection
*****************************************************************************/
#define
hyplnk_EXAMPLE_LOOPBACK
/*****************************************************************************
* Select number of lanes allowed
*****************************************************************************/
//#define hyplnk_EXAMPLE_ALLOW_0_LANES
//#define hyplnk_EXAMPLE_ALLOW_1_LANE
#define
hyplnk_EXAMPLE_ALLOW_4_LANES
/*****************************************************************************
* Select a serial rate
*****************************************************************************/
//#define hyplnk_EXAMPLE_SERRATE_01p250
//#define hyplnk_EXAMPLE_SERRATE_03p125
#define hyplnk_EXAMPLE_SERRATE_06p250
//#define hyplnk_EXAMPLE_SERRATE_07p500
//#define hyplnk_EXAMPLE_SERRATE_10p000
//#define hyplnk_EXAMPLE_SERRATE_12p500
/*****************************************************************************
* Set if each endpoint has its own hyperlink clock
*****************************************************************************/
#define
hyplnk_EXAMPLE_ASYNC_CLOCKS
/*****************************************************************************
* Set to perform equalization analysis
*****************************************************************************/
#define
hyplnk_EXAMPLE_EQ_ANALYSIS
/*****************************************************************************
* Set to enable an error interrupt on uncorrectable serial errors
*****************************************************************************/
#define
hyplnk_EXAMPLE_ERROR_INTERRUPT
Inside Hyplnkplarcfg.h, make sure
#define hyplnk_EXAMPLE_HYPLNK_REF_KHZ 156250
Inside HyplnkLLDIface.c
change
for(i=0; i < hyplnk_EXAMPLE_MAX_LANES; i++)
{
CSL_HyperlinkSerdesLaneEnable(baseAddr,
i,
CSL_SERDES_LOOPBACK_ENABLED, ==========> not disabled!!
lane_rate);
}
when doing loopback.
Then rebuild the test application. Before loading and running, you need to change the EVM use 156.25 MHz reference clock instead of default 312.50 from BMC console:
BMC>hwdbg cmd clkreg show
BMC>clkreg 3.6 0x03
Then, load the code and run, loopback worked for me.
Regards, Eric