Dear,
Device: TMS320C6657
I have noticed that there is inconsistency value between sprabi2b.pdf and sprabi1a.pdf.
Question:
Which is correct value of skew for DDR3 data line? I think the value of sprabi1a is too strict. Therefore I think the value of sprabi2b is correct. Am I right?
sprabi2b - Hardware Design Guide for KeyStone I Devices
In page 34 says:
4.2.3 SDRAM Routing Guidelines - Data Lines Total length from device to each SDRAM of all respective DQ and DM signals within a byte lane should be skew matched to the DQS line ± 0.03937 inch (1.00 mm).
sprabi1a - DDR3 Design Requirements for KeyStone Devices
In page 32 says:
4.3.1.6 Routing Rules - Data Lines - [SDRAMs] Total length from DSP to each SDRAM for all respective DQ and DM signals within a byte lane should be skew matched to the DQS line ± 10.00 mils (0.50 mm). DQS to DQS# skew shall be ≦ 10.00 mils (0.254mm).
Following are mm aligned:
sprabi2b says, ±0.03937inch = ±1.00mm.
But,
sprabi1a says, ±10.00mils = ±0.01inch = ±0.254mm
Best regards,
Okayama
