Paul, I am not sure what is your intended use case. Core and task affinity assignment is only supported on Cortex A and Cortex M platforms that support SMP (symmetric processing) mode. Cortex R5 (MCU) only supports lockstep (core1 is diagnostic core for core0) and split mode (both cores are independent) operations. If your objective is to use core 1 for processing then you need create a independent SYSBIOS application for that core and ensure there is no overlap of resources in the two applications unless there is shared memory setup. Check the E2E discussion here: https://e2e.ti.com/support/processors/f/791/t/814666 Regards, Rahul
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