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Forum Post: RE: omap l138 sata dma engine startup problem

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Problem solved.

I've concluded that the P0TFD busy should normally get cleared when the SUD (spin up device) bit is set in P0CMD as a result of the automatic COMRESET initialization.  My issue was that this COMRESET never completed because the receive side differential signal had it's polarity incorrectly wired on the schematic.  Note that this was easily fixed by setting P0PHYCR RXINVPAIR to 1 which inverts the receive polarity.


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