In one of the devices phy the issue sill occurs, but not always.
It turned out that phy is being reseted by fpga, so I checked fpga source code and found out that reason for this can be wrong "clock2_pll_lock" state.
I checked it on osciloscope and this signal state was wrong (but not always), and fpga was reseting phy with ~900kHz frequency. When heat sink is put on CDCE62005, problem occurs more often.