Through trial and error, I determined the following:
- When the magic number DOES NOT include _PLL_, the PLL registers not modified at all.
- When the magic number DOES include _PLL_, the PLL registers are modified as follows:
- PLL1 is always configured as M=9,N=0 to produce 432 MHz (based on 24 MHz input clock)
- DIV4 is always configured as 3 to produce 108 MHz for SYS/EDMA/PER (based on 24 MHz input clock)
- AEMIF clock will always be 108 MHz / 2, or 54 MHz (based on 24 MHz input clock)
- PLL2 is configured according to the boot descriptor. The values are M and N are written directly into the respective registers without modification.
So now I have a new problem. I am running a 216 MHz part, but when using a _PLL_ magic number the SYS/EDMA/PER clock is always 108 MHz (based on 24 MHz input clock) while the maximum in the datasheet is 865 MHz. It seems as though I cannot use the _PLL_ magic number without exceeding the maximum SYS/EDMA/PER clock!
Any comments?