Hi Mike,
I've asked the boot rom support team to join the thread to see if we can get some additional information on where the data should end up. Have you been able to capture more information on the temperature where the failure occurs? The component has been tested at temperature so we need to investigate the stability of the SPI interface when the temperature is high. Can you do a read test of the SPI memory when the device is at a high temperature to see if you can read the memory correctly? Can you also capture the read from the SPI memory when the reset occurs at the higher temperature? I want to see the signal integrity so please capture the clock and data as close to the SOC as possible.
What is the C6654 doing when you reset the part? Have you set the PLLs so that the core is running at full speed? You should also probe the CVDD at the C6654 when the reset is applied. We have seen some boards with an insufficient PDN design that will experience an overshoot or undershoot in the CVDD when the part throttles from full speed to bypass at a reset.
Regards, Bill