Forum Post: DM36x PLL2 Initialization

Hi experts,

DM36x UBL in IPNC RDK has following codes.

Uint32 DEVICE_PLL2Init()

{

                ……..

     UTIL_waitLoop(150);

      /*Wait for PLL to LOCK */

      while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000));

     UTIL_waitLoop(4100);

                return E_PASS;

}

BTW, ARM subsystem User’s guide says that bit[27:25] indicates the LOCK status. If it’s correct, then upper code should use 0x0E000000. Which one is correct?

 PLLC2_CONFIG

bit 27-25 : 111b=locked

bit 24 : reserved

Thanks,

Devin