Ok, the sequence appears to be ok.
That said, if there's other activity going on the MFENCE will block operation until that activity has completed and thus give you a longer than expected time.
Sounds like you're using the QMSS which if it's active in moving data it could potentially stop traffic until all activity has completed prior to allowing the CorePac to continue on, and thus effectively extend the time of the WB/INV process.
What are your UCARBx and CPUARBx register values set to? You may want to change the UCARBU maxwait to 2 or 4 and see what kind of improvement you get as well, if something is blocking it, this should guaranty much more will get through.
Best Regards,
Chad