HI Bill,
This bandwidth is sufficient for our application. As you noted the Xilinx on SP605 will be an endpoint configuration and the C6655/6657 will need to be configured as a root point/root complex. I am moving forward with my original thought of generating a simple impedance matched daughter card that will plug onto 6657 AMC edge card finger. I do not believe any of the available adapter cards really provide what we need. Basically I plan to have a single lane R/.A PCB edge connector on one end of daughter card to interface to the SP605 EVM and a 170 pin R/A PCB edge connector on other end of daughter card to interface to 6657 DSP EVM AMC edge finger.. I currently am planning to connect a single diff pair Transmit and Receive lane from DSP to single Gen1 lane available on SP605. Basically 4 signals. The other 2 signals would be diff pair PCIE_REF_CLK. First I would like to confirm that this minimum subset of connections would be adequate between SP605 endpoint and 6657 root complex to properly negotiate a link and pass date successfully with both devices configured correctly. If yes...my next question revolves around PCIE_REF_CLK. After looking at this signal on DSP side, it appears that either a Ref clock input or internally generated 100MHz PCIE diff clock could be generated and passed to DSP PCIE diff clock input which would pass to PCIE Express Core. It does not appear that internally generated PCIE clock on 6657 EVM could be passed to AMC edge connector and actually passed over to SP605 EVM...Did I miss something or is this correct. On the SP605 end, it appears that the PCIE clk is also an input only as well which is then passed through a Jitter Attenuator. Basically what I am saying is that both PCIE_Ref clocks to both boards appear to be inputs only and no way to pass PCIE clock from on board clock generator on DSP. If this is the case, then I need to put a low jitter 100MHz clock generator to distribute to both EVMs on what I was hoping to be a fairly simple daughter card to interface between boards. Please confirm and/or let me know what I am missing in my thought process.