Will,
Joking: If you read every word of the five User Guides and the datasheet, you would already know this.
The good part is that all the information is out there. The saving grace is that the pdf searches and desktop search tools can eventually find these things.
I started with the datasheet, which has the PLL Topology in Figure 5-9 on page 88 / 271. It is an important reference, but did not have the answer.
Then I went to the Timer64 User Guide sprufm5, which is also included in the TRM spruh79a. In the TRM, Section 29.2.1.2.1 Using the Internal Clock Source to the Timer shows the clock selection mux in Figure 29-2 on page 1400 / 1752. The next section, 29.2.1.2.1 Using the Internal Clock Source to the Timer says to see the PLLC chapter, where you can find the PLL Topology figure again, renamed Figure 7-1 PLLC Structure. The next page has Table 7-1 System PLLC Output Clocks which shows that PLL0_AUXCLK drives Timer64P0/P1. Then on page 121 / 1752 has Figure 6-1 Overall Clocking Diagram, which also shows PLL0's AUXCLK driving Timers 0 and 1.
Whew!
With that knowledge, you can go back to the datasheet or the TRM Figure 7-1 PLLC Structure on page 135 / 1752 to see that AUXCLK comes from the input clock source from your crystal or input clock oscillator on OSCIN.
And that should be the right answer.
Not exactly trivial to find, is it? So a lot of people will thank you for asking.
Regards,
RandyP