Our design has IBL booting core0 from SPI NOR. Core0 then starts several control tasks and waits for an external host to download (through UART in FPGA linked via SRIO) elf images to run on cores 1-7. Core0 then manages cores 1-7 via MessageQ IPC. The loader is derived from the elf loader code in the IBL and the core reset/run code in the MAD utilities. Everything works excect IPC between the cores when loaded via this scheme.
If we skip the download via UART and use CCS to load the elfs in all 8 cores, IPC works.
If we use MAD loader to load the elfs in all 8 cores, IPC works.
If we use IBL or CCS to boot a custom loader (who's basic function also resides in our "real" core0 code) to load cores 0-7, IPC works.
In trying to debug this, we have isolated it to IPC Notify failing somehow. We took the example notifiy_muticore and modified it such that we can do the follow depending on how it is configured:
A. Load cores 0-7 L2SRAM with CCS as in stock example. IPC works.
B. Load cores 0-7 L2SRAM with MAD. IPC works.
C. Load core0 L2SRAM with code that has both the IPC example and loader functions. Core0 loads cores 1-7 L2SRAM and the continues on to run the IPC example. Cores 1-7 run but IPC does NOT work.
D. Load core0 DDR3 with code that has only loader function. Core0 loads cores0-7 L2SRAM, starts cores1-7, then jumps to the entry address in core0 L2SRAM. IPC works.
I also tried several other scenarios in addtion to A-D. They also did not work.
So, many scenarios work. But the one that we need for our real system does not.
Why does IPC fail when core0 loads cores1-7 and then continues on to participate in IPC?
Any help is appreciated. I could post my example if desired.
Versions:
IPC: 1.25.0.04
CCS: 5.3.0.00090
Compiler: v7.4.2
SYS/BIOS: 6.34.2.18
MCSDK PDK TMS32C6678: 1.1.2.6
XDCtools: 3.24.5.48