I have some problem setting the registers for the DDR3 Leveling
i've seen that after the inizialization the IFRDY bit in DDR3 Memory Controller Status Register always remains 0 and i think is a problem of the initial leveling settings
I'm trying to use the spread sheet DDR3_PHY_Calc. I should write 8 clock lane lenght but i have only 2 of them and all value in column G from row 12 is marked in red. (I'm using a DDR3 SDRAM SODIMM MT16JTF1G64HZ – 8GB so i have only CK0 and CK1 pairs)
This is my spreadsheet
(Please visit the site to view this file)
Any advice?