I'm trying to optimize the SRIO inizialization but i still have problem to configure some registers:
SP_LT_CTL
SP_RT_CTL
PLM_SP(n)_DISCOVERY_TIMER
Port (n) Silence Timer
PRESCALAR_SRV_CLK
The problem is that i have no idea of what value i should consider for the two internal clocks SRV_CLK and IP_CLK and how they are related to the SRIO CLOCK (=SYSCLK/3)
I've read some other discussion but i still haven't found the answer...
Could anyone help?