HDVPSS can handle maximum of 1920 pixels per line. Maximum pixel clock support for capture and display is upto 165MHz.
From codec prospective, some of the codecs supports resolution upto 4kx4k. You could check this here(encoder/decoder user guides) for different decoder/encoders:
A little know fact is that a small FPGA fitted in front of each of HDVPSS Video Input ports and a bit of magic update to TI's CODEC will enable DM8168 to stream two (2) channels of SuperHD - like 2560x1600 or 2048x2048 - @ 20FPS.
The same principle could apply for even larger frames, effectively only limited by the number of slices the FPGA can divide into the limitation of the 165MHz sped of HDVPSS, but the Frame Rate will be reduced. Estimate is that 4096x4096 would stream at around 10 FPS for one channel.