Hi Lukasz,
I performed the DirectIO throughput tests using the throughput example found in the PDK. This example project can be found a the following location after you install the MCSDK:
<install directory>\pdk_C6670_x_x_x_x\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject
I configured the example in the following way:
- Internal loopback (this would ensure full duplex transmission)
- 1 x4 port operating at 5 Gbps per lane
The results for both the NREAD and NWRITE tests yielded similar throughput values as presented in the Throughput User Guide. Note that the data presented in this guide was captured using L2 memory endpoints. I plan to run these same tests using MSMC memory to see if different results are achieved.
Have you reached out to Xilinx about this issue? Based on RY's post above it sounds like the 5 Gbps x4 link might not be supported on their end. Please let us know what you find out.
Thanks,
Clinton