Forum Post: RE: timing model for the DDR memory controller which is inside the DM8148

Thanks, Steve for highlighting possible limitations while using these IBIS models with HyperLynx and its DDR Wizard.

I would still be interested if we can have atleast  waveforms and timing information with respect to the DDR2/3 controller of 8148. I am unable to find it in the datasheet, which mainly seems to focus on layout/routing recommendations for the DDRx interface and has very little information on the Electrical/timing information. Is it available only under NDA? 

One more thing which i came across in the web - JEDEC spec is targeted only for DDR devices and DDR controller spec is outside it purview. Is this true? In that case, there might already be a need for the detailing timing diagram/parameters for our design validation?

Regards,

KS