Forum Post: questions about L1D, MAR and cache coherence on C6657

We use C6657 to talk with our host processor through PCIe. We enabled cache (L1D, L1P and L2). We put the communication buffer in a buffer in none-Cache DDR by zeroing MAR128. Do we have to manually maintain cache coherence for L1D during PCIe communication (write back when core write and invalidate before core read?)

SPRUGW0b-1 section 4.4.4 says that "L2 memory includes a set of registers to define the cacheability of external memory space". Does that mean that MARn only affects L2 cache, and if we use data range with corresponding MARn=0, we still have to manually control L1D?

thanks

Weichun