Hi TI engineer:
We have an application to connect C6657 to FPGA in 2 1xport. Now it's not successful,for investigating the problem,can you tell me:
1.if I config port 0 1 2 3 to path mode0, then I divide SRIO to four 1x port,isn't it?
2.If I config port 0 1 to path mode0,then I divide SRIO to two 1x port, and what I do to port 2 3 will be unmeanningful,isn't it?
3.when srio works in 2 or 4 1xport, each port can connect to target, they don't influence on each other at all, isn't it?
Look forward to reply, thank you very much!