Hi,
It looks like your remote register memory block(0x80 ~ ) is blocked by memory blocking. please check your GEL file or other memory mapping setup or MPAX if you block that memory access from any Cores or not. normally, we don't recommend to check remote registers through CCS memory window, because it may half the system if the data transaction with remote is failed and you may have to POR reset in that case and that's why we normally block the remote area memory by using GEL file memory map setup.
your link is alive and link state register bit 8 is up. that means your SERDES training is finished but you still can see other garbage in the register which means not good training result. If training is perfectly done. it should show 0x00000100. check your board design if sideband signal quality is good or not. also check your SERDES signal quality by checking EYE view. you may need get better quality of clock and signal. Hyperlink is very sensitive interface. you'd better reduce the trace length as best as you can (less than 4 inch on the board) your final workaround will be set Hyperlink as quad lane mode always and do not make it have flexible link speed while link initialization process is fully done, because quad lane mode use full power and make SERDES try its best to detect the signal.
Regards,
Albert