The above document states in numerous places that the total signal length of the RTCK etc should not be greater than 3”. We have implemented a system similar to the evaluation card where either the 60 pin header can be used or simple JTAG header via IC switches can be used to access the DSP debug. With this we are struggling to meet this 3” restriction, we currently have 4.5”. I have looked at this on the evaluation layout to see how it was achieved and it on this PCB the signal length is 9.3” and it works. Can anyone comment on this?
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thank you.