Steven,
memory_transfer() is only called from one thread. We have 4 SWIs. The highest priority SWI is a SYS/BIOS clock instance which only keeps a counter and calls SWI_post() for the other 3 SWIs. The SWI that calls memory_transfer() is the next highest priority SWI, so if it is preempted it will only be for however many clock cycles SWI_post() takes. Is there any problem with this setup?
One thing we have found out is that most of the time when memory_transfer() is called the bit that will be later polled in IPR is already set prior to calling CSL_edma3ParamSetup(). After CSL_edma3HwControl() is called it is always cleared though, so somehow it is set between calls to memory_transfer(). Is there something other than the QDMA transfer completing that could cause this bit to be set?
With our current setup, is calling CSL_edma3ParamSetup() sufficient to initiate the transfer and there's no need to call CSL_edma3ParamWriteWord() in memory_transfer()?
Also, with using a different shadow region for each core, is it ok to use the same TCC value on each core?
Regards,
Chris