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Forum Post: RE: TMS320VC5506PGE EBSR register issue

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Thank you for the detail description of issues. I have a few questions to further understand the issue.

Earlier this week, we found that the problem *only* occurs if we write the EBSR register. Specifically, it only occurs if we leave '11' in the Parallel Port Mode bits (i.e. do not change them). We have found that it is safe to write the EBSR register if we write '00' in the Parallel Port Mode bits.

Q: Since you boot from I2C, GPIO is 0 at reset thus Parallel Port Mode bits are "11" after reset without any write. Does problem exist on current build and previous build? Is this write occur in previous build which has no issue? Can you provide the symbolization of curent (fail) and previous (pass) devices? This can help tracking the fabrication data.

So in summary:

  • All is good if the EBSR register is not written at start-up.
  • All is good if the EBSR register is written at start-up such that the Parallel Port Mode bits are changed to '00'.

Q: When exactly is this write occur since I2C boot requires GPIO0=0?

  • Failures will occur (but only on select ICs) if the EBSR register is written at start-up such that the Parallel Port Mode bits are NOT changed from '11'.

Note that the lockup failure does not occur when this line of code is executed, and the chip may run fine for hours. The failure can be easily triggered *anytime* later by light pressure to the top of the IC case (or other stress such as slightly flexing the PCB), but ONLY IF this line of code to write the EBSR register was executed back at startup time.

Thus we are looking for a much more detailed explanation as to why the IC boots into a documented "Reserved" mode in this usage scenario, and why changing this mode is documented simply as "not recommended" without further clarification.


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