[quote user="David George"]
1.
I note that pathmode = 4 in the example,it means that you can config full lane for transfer.
pathmode = 4; //means that one port 4x
for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, pathmode);
But why such config can work successfully? I don't think you can config the SRIO
for one port 4x mode on DSPC-8681E.As I know,DSP0(c6678) has 4 lanes .But
in 8681 DSP0 only use one lane to connect DSP1 and use another lane to connect
DSP3.I am not sure DSP0 and DSP1 use lane0 or lane1 or lane2 or lane3.So do DSP0
and DSP3.But one thing is sure that the lane number which DSP0 and DSP1 connect with
cannot be four.Because DSP0 only have four lanes,the four lanes may be used for DSP1 and
DSP3.But four lanes of DSP0 cannot totally be used by DSP1.So,I believe that you cannot
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 4) to set all the ports.Because DSP0 and
DSP1 cannot use all the lanes for transfer. Transfer Pair (DSP0-DSP1) and Transfer Pair (DSP0-DSP3)
will share all the four lanes.Anyhow,I don't believe you can set pathmode = 4.
In fact ,such config pass the SRIO test .So why?
[/quote]
Yes Path_mode = 4 means 4x port. If you spend some time reading the RapidIO Serial specification, you will see that the state machines do allow for a 4x capable port to run in 1x mode. It is a fall back, if 4x operation can't be established because of a bad lane for example, the 4x port can establish a 1x port on either lane 0 or lane 2.
[quote user="David George"]
Another hand,I try to modify pathmode = 0. it meas that four 1x ports.
I believe pathmode = 0 should be suitable and wright.Still the reason I confirm above that
DSP0 and DSP1 only connect each other with one lane,Assume it is lane0.So pathmode =0.
At least it should be 1x port not 4x port.But the result is disappointed.When I modify code like below
for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);
The example cannot pass the test.So, Where make mistakes? Does my guess standup?
Where can I get the schematics of DSPC-8681E,So I can know how many lanes and which lanes
do DSP0 and DSP1 use .So I can config SRIO port correctly .How to treat this problem?
Who leads the bad result?
[/quote]
Not sure if you are seeing errors, or if the test you are running in this setup is not sending the packets to the write port. The schematics would have to come from Advantech directly.
Regards,
Travis