Thanks, Ian. Now the bigger issue with all of this is signal integrity. Along with having fairly long (~1in), thin (3.5mil) traces to these power pins, the decoupling cap was also placed ~1in away. Combined with the higher inductance of the thing 3.5 mil trace width, there's a concern that the signals powered by these signals will have SI issues.
Here's a list of the pins that concern us:
| Pin Name | Pin Function | AVG Current | Potential Resolution |
| AVDDA1 | SYS_CLK PLL Power Supply | 50mA max | Solder a 0.01uF (?) decoupling cap at each pin. |
| AVDDA2 | DDR_CLK PLL Power Supply | ||
| AVDDA3 | PASS_CLK PLL Power Supply | ||
| VDDR2 | PCIe SerDes Supply | ||
| VDDR3 | SGMII SerDes Supply | ||
| VDDR4 | SRIO SerDes Supply |
So we're hoping to find out:
1) Will the signals that are powered by these pins (internal clocks, DDR3 signals, PCIe link, SGMII link, SRIO link) be operable? eg. Will the DM8168 that's connected to this C6678's PCIe bus be able to communicate with it? Will the DDR3 memory operate?
2) Does it get any better if we do our post-assembly "fix" and solder a decoupling cap at each of these pins?
3) Do you have a method to simulate any of this? We don't know the internals of the parts, so it is very difficult for us to simulate.
Also know that this is an alpha-level prototype - we certainly will fix this in the next spin, but we would like some good confidence things will work (or not), so we can better evaluate what our next steps are.
Thanks!
-Bill