Hi,Travis:
About the CSL_SRIO_SetPLMPortPathControlMode,I want to say more .
I run the example in the pdk1.1.2.5 for SRIO Throughput on DSPC-8681E.Although
I have passed the test and the result give the performance.But I cannot understand
why I can pass the test.By the way,I modify some obvious places such as from loopback
to Normal (device to device ) and make example suitable for DSPC 8681E to move
data between DSP0 and DSP1.Luckily, I load consumer out to DSP0 and load producer
out to DSP1 and run successfully. But I don't know why?It seems unreasonable .
1.
I note that pathmode = 4 in the example,it means that you can config full lane for transfer.
pathmode = 4; //means that one port 4x
for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, pathmode);
But why such config can work successfully? I don't think you can config the SRIO
for one port 4x mode on DSPC-8681E.As I know,DSP0(c6678) has 4 lanes .But
in 8681 DSP0 only use one lane to connect DSP1 and use another lane to connect
DSP3.I am not sure DSP0 and DSP1 use lane0 or lane1 or lane2 or lane3.So do DSP0
and DSP3.But one thing is sure that the lane number which DSP0 and DSP1 connect with
cannot be four.Because DSP0 only have four lanes,the four lanes may be used for DSP1 and
DSP3.But four lanes of DSP0 cannot totally be used by DSP1.So,I believe that you cannot
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 4) to set all the ports.Because DSP0 and
DSP1 cannot use all the lanes for transfer. Transfer Pair (DSP0-DSP1) and Transfer Pair (DSP0-DSP3)
will share all the four lanes.Anyhow,I don't believe you can set pathmode = 4.
In fact ,such config pass the SRIO test .So why?
2.
Another hand,I try to modify pathmode = 0. it meas that four 1x ports.
I believe pathmode = 0 should be suitable and wright.Still the reason I confirm above that
DSP0 and DSP1 only connect each other with one lane,Assume it is lane0.So pathmode =0.
At least it should be 1x port not 4x port.But the result is disappointed.When I modify code like below
for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);
The example cannot pass the test.So, Where make mistakes? Does my guess standup?
Where can I get the schematics of DSPC-8681E,So I can know how many lanes and which lanes
do DSP0 and DSP1 use .So I can config SRIO port correctly .How to treat this problem?
Who leads the bad result?
Best Regards!