Quantcast
Channel: Processors
Viewing all articles
Browse latest Browse all 123829

Forum Post: RE: DSK6455 problems porting from CCS 3.1 to CCSv5

$
0
0

David,

Since this thread has been discussing EDMA3 and McBSP interrupts, we have not discussed code optimization. The workshop material I referenced earlier shows how to use the compiler most effectively to optimize code, and it may even use an FIR is its sample lab exercises (it has been a while since I looked at the class in detail).

There are a lot of things that have not been discussed in the thread that would affect your operation. The simple things that make the code run faster are:

1. Turn on optimization by using the Release build configuration instead of Debug. This can have a 10x effect on code performance.

2. Turn on cache. By default, the L1 caches are "on" and the L2 caches are "off", which is adequate but using L2 cache can help. Also by default, all external memory is set to be uncacheable; this is changed by setting the MAR register bits to 1 for the relevant external memory addresses and can be done by CSL or by DSP/BIOS.

3. For the FIR filter, use the DSPLIB function to get the best performance in the inner loop. No need to code it yourself or worry about using the keywords and pragmas to tell the compiler how to optimize the code.

4. Use EDMA3 for data movement. This is the most work of all of these steps only because it has to be done by you in your code with insight into the system's operation.

You definitely do not want to try to write C64x+ assembly code nor second guess the compiler. But reading the assembly code can tell you quickly if the compiler is optimizing well. You can search for the FIR function and see if there are a bunch of NOPs (bad) or an SPLOOP (good).

Because the C64x+ is highly optimized for doing things like an FIR, you can get the performance down to just a few clock cycles per tap, conceivably less than 1 cycle per tap depending on all of the above numbered methods. The C64x+ has 8 RISC CPUs that operate in parallel. I would put it up against any of the Brand X or Y or Z DSPs, for each generation of DSPs.

I am sorry for the trouble you have had with this design, and wish you well for the project's success. If there is anything else you would like to pursue on this, please let us know. TI wants to be part of your success.

Regards,
RandyP


Viewing all articles
Browse latest Browse all 123829

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>