Forum Post: RE: Aboult the throughput of keystone's MSMC

Hi Rajasekaran

Thank you for a reply!

>All the banks can be accessed simultaneously but the read & write operation can not be at the same time. 

I understand that the 4 banks MSMC SRAM can be read  simultaneously or  written simultaneously.

Is that correct?

But if MSMC SRAM has 256bits per bank， why the read & write operation can not be at the same time?

Is there a more detailed description?

Thanks!

Yin