The first step in the execution of the SIR is to read the Timer Interrupt Aggregation Flag Register (TIAFR, 0x1C14) and check bits 0 and 1 to determine source of the timer interrupt .
In regards to your second question, I set a breakpoint at the first line of the timer ISR and observed the INTM bit set to one. This confirms SWPU073. Upon leaving the ISR and returning execution to the main loop, I observed the INTM bit restored to 0.
However, I was able to fix my problem by changing the way I write a 1 to the TIAFR to clear the respective flag.
The previous code (as shown above) used a logical OR to set the bit (TIAFR |= 0x01). Upon looking into the CSL code, I observed the value use to set the respective bit was directly written into the register (TIAFR = 0x01;). It's somewhat counter intuitive to me to overwrite a register value instead of ORing in the bit I want to set, but I understand I can get away with it since this register is not effected with writes of zero to any bit.
I guess there was some kind of timing issue going on since the OR line of code causes a read and write of the memory location while the write is just that, a direct write.
Any thoughts why I can't get away with the OR to set that bit?