It seems that TI gives conflicting information between the TRM and the Datasheet (sprs685d). The TRM on pages 2227 -2228 says that the memory configurations in the table are valid per chip select. Could someone at TI please verify?
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It seems that TI gives conflicting information between the TRM and the Datasheet (sprs685d). The TRM on pages 2227 -2228 says that the memory configurations in the table are valid per chip select. Could someone at TI please verify?