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Forum Post: RE: PLL mult/div Limitations DM368

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Ivan,

if I understand Table 3-9 (SPRS668C, p.61) correctly, for 27 MHz input clock the suggested values for PLL1 are:

PLLM=340,

PREDIV = 0,

POSTDIV=26,

so that 

PLL1OUT= 27 MHz / (PREDIV + 1) * 2 * PLLM / (POSTDIV + 1) = 27 / 1 * 2 * 340 / 27 = 680 MHz.

I find it very doubtful that those settings will work because they result in the PLL clock (before the post-divider) of over 18 GHz. 

That's why I was (and still am) looking for the answer from TI: what are the limits on the PLL clock frequency (both upper and lower)?

As for DDR settings: we've double and triple-checked those. We also ran a temperature test on our boards, up to +70C. Not a single problem there. Our system is not "unstable", it's very stable, just the speed varies between the boards. If there was a DDR problem, wouldn't we see data and code corruption? We don't see anything like that. On "bad" boards compression takes longer than on "good" ones, that's it.

Regards,

Alexander.


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