Hi,
I'm sorry, I made a mistake for the Workaround 3 in Advisory 9.
For Workaround 3 in Advisory 9, the Full Automatic Leveling with the Incremental Leveling is used for the latest KeyStone devices. The details are described in Application Note below.
KeyStone DDR3 Initialization (Rev. A)
http://www.ti.com/lit/an/sprabl2a/sprabl2a.pdf
3.3 Full Automatic Leveling
In this leveling mode, Incremental leveling is used for the Read DQS Gate Training and the Read Data Eye Training and can work in substitution for Full Automatic Leveling that has the Read Data Eye Training issue.
For the more optimum leveling, this leveling mode should be used.
Is my above-mentioned understanding correct?
Please give me an answer for my questions as soon as possible.
[quote user="Daisuke Maeda"]
The timeout register bits in the DDR3 Memory Controller Status Register can be read to verify that the leveling completed as expected.
DDR3 Memory Controller for KeyStone Devices User's Guide (Rev. C)
http://www.ti.com/lit/ug/sprugv8c/sprugv8c.pdf
4.2 DDR3 Memory Controller Status Register (STATUS)
Can the reading these bits ensure the detection of the failure of the leveling? Should the data written be verified? If so, how should it be verified? Should all addresses be verified?
[/quote]
[quote user="Daisuke Maeda"]
For the DDR3 Register values and the DDR3 PHY initial values, two spreadsheets below are used.
DDR3-Register-Calc-v4
http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/6013.DDR3-Register-Calc-v4.xlsx
DDR3-PHY-Calc-v10
http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/639/8130.DDR3-PHY-Calc-v10.xlsx
Are these spreadsheets the latest version?
[/quote]
Your prompt reply would be appreciated.
Best regards,
Daisuke